1. Field of the Invention
This invention relates to processors. More specifically, this invention relates to processors having an instruction decoder for decoding multiple instructions simultaneously and an instruction buffer circuit that converts instructions from a memory alignment to an instruction alignment for preparing instructions for decoding in parallel
2. Description of the Related Art
Advanced microprocessors, such as P6-class .times.86 processors, are defined by a common set of features. These features include a superscalar architecture and performance, decoding of multiple .times.86 instructions per cycle and conversion of the multiple .times.86 instructions into RISC-like operations. The RISC-like operations are executed out-of-order in a RISC-type core that is decoupled from decoding. These advanced microprocessors support large instruction windows for reordering instructions and for reordering memory references.
In a microprocessor having a superscalar architecture, multiple computer instructions are transferred from a memory, decoded and executed simultaneously so that the execution of instructions is accelerated. A RISC-type processor typically has no problem decoding multiple instructions per cycle because all instructions are the same length. When all instructions are the same length, multiple instructions are easily transferred from memory in parallel because the memory locations of all instructions is known or readily ascertainable, allowing multiple instructions to be simultaneously transferred to instruction registers inside the processor. However, many microprocessors and computers, such as .times.86 processors that have a complex instruction set computer (CISC) type architecture, use a CISC-type variable-length instruction set in which different instructions have different instruction lengths, varying from one byte (8 bits) to fifteen bytes (120 bits) in length. Thus the locating of multiple instructions is a sequential process, and therefore slow process, because one instruction must be decoded to determine the length of the instruction before the starting location of the next decodable instruction is ascertained.
Decoding of multiple .times.86 instructions in parallel has additional difficulties. One difficulty is that instructions are supplied to a processor from memory in a memory alignment. The decoder operates on the instructions in an instruction alignment. To rapidly decode instructions in parallel, the alignment of the instructions must be rapidly converted from the memory alignment to the instruction alignment.
What is needed is a system and method for accessing a plurality of variable-length instructions and preparing the variable-length instructions for decoding of multiple instructions in parallel. One aspect of this system and method is a technique for determining the starting point of an instruction and, from this determination, converting instructions from a memory alignment to an instruction alignment.